The present invention relates to integrated circuit devices, and more particularly to integrated output driver circuits.
Integrated circuits typically include output drivers therein for driving on-chip and off-chip loads. To reduce power (Vdd) bounce and ground (Vss) bounce problems in integrated circuits, circuit designers have developed techniques to slowly turn on the output drivers to minimize power and ground bounce effects. Such techniques typically result in a trade off between operating speed and power and ground bounce. One conventional technique for minimizing power and ground bounce in an output driver is illustrated by FIG. 1. The output driver of FIG. 1 includes an NMOS pull-down transistor N2 having a drain electrically coupled to an output OUT of the driver. When the NMOS pull-down transistor N2 is turned on, the output OUT is pulled low to Vss. When the NMOS pull-down transistor N2 is turned off, the output OUT is disposed in a high impedance state. The gate of the NMOS pull-down transistor N2 is controlled by a driver control circuit. This control circuit includes a totem pole arrangement of a PMOS pull-up transistor P1, a resistor R1 and an NMOS pull-down transistor N1, connected as illustrated. A gate of the PMOS pull-up transistor P1 and a gate of the NMOS pull-down transistor N1 are electrically connected together and responsive to an input signal IN.
In the output driver of FIG. 1, the resistor R1 is included in order to slow down the rate at which the NMOS pull-down transistor N2 is turned on in response to a logic 0 input signal IN. The inclusion of the resistor R1 slows down the driver by slowing down the rate at which the voltage at the gate of NMOS pull-down transistor N2 transitions from 0 volts to Vth volts (where Vth is the threshold voltage of the NMOS pull-down transistor N2). However, the inclusion of the resistor R1 does not significantly improve the ground bounce characteristics of the driver. The slow down in speed of the driver is particularly serious when Vdd is relatively low. In contrast, when Vdd is high, the sinking current provided by resistor R1 increases and causes the voltage at the gate of the NMOS pull-down transistor N2 to ramp up faster and this increases ground bounce. Thus, the use of a resistor makes speed slower at low Vdd and ground bounce greater at high Vdd. Moreover, at low temperature, the sinking current through resistor R1 increases (because the resistance of resistor R1 decreases) and the drain-to-source current through the NMOS pull-down transistor N2 increases. This makes ground bounce worse at lower temperatures and speed slower at high temperatures. What is needed, therefore, are driver circuits having excellent ground and Vdd bounce characteristics that are at least substantially independent of changes in Vdd and temperature.
Integrated output driver circuits according to embodiments of the present invention have sourcing and sinking current characteristics that reduce power (Vdd) and ground (Vss) bounce effects by making the dl/dt characteristic of the sourcing current to a load and/or sinking current from the load more nearly uniform and substantially independent of Vdd and temperature. Improved speed characteristics can also be achieved using capacitive bootstrapping to quickly turn on an NMOS pull-down transistor, which controls the sinking current from the load, and/or PMOS pull-up transistor, which controls the sourcing current to the load.
In particular, an integrated driver circuit according to one embodiment of the present invention includes a first driver transistor and an output signal line electrically coupled to a first current carrying terminal of the first driver transistor. The first driver transistor may be an NMOS pull-down transistor having a drain connected to the output signal line and a source electrically coupled to a reference power supply line (e.g., Vss). The first driver transistor may also be a PMOS pull-up transistor having a drain connected to the output signal line and a source electrically coupled to a positive power supply line (e.g., Vdd). The driver circuit also includes a preferred driver control circuit. According to one aspect of this embodiment, the driver control circuit has a switchable pull-up path therein that extends between a gate of the first driver transistor and the positive power supply line. This switchable pull-up path includes a depletion mode transistor (NMOS or PMOS) having a first current carrying terminal electrically coupled to the gate of the first driver transistor. The depletion mode transistor may be a buried channel device. The gate and the first current carrying terminal of the depletion mode transistor are electrically connected together. The switchable pull-up path may also include a PMOS pull-up transistor having a drain electrically coupled to a second current carrying terminal of the depletion mode transistor and a source electrically coupled to the positive power supply line.
To improve speed characteristics, a bootstrap capacitor is provided having a first electrode electrically connected to the second current carrying terminal of the depletion mode transistor and a second electrode electrically connected to the first current carrying terminal of the depletion mode transistor. In particular, preferred high speed characteristics can be achieved by sizing the capacitor so that its capacitance is in a range between about 0.75 and 1.25 times Cideal, where Cideal=|Vth|(Cin)/(Vddxe2x88x92|Vth|), Vth is a threshold voltage of the NMOS pull-down transistor, Cin is an input capacitance of the NMOS pull-down transistor and Vdd represents a magnitude of a power supply voltage applied to the positive power supply line. The on-state characteristics of the depletion mode transistor are also chosen so that its ldsat characteristic has a right positive temperature coefficient (i.e., dldsat/dT is positive). The value of the positive temperature coefficient is sufficient to at least substantially compensate for a reduction in majority carrier mobility in an N-type inversion layer channel of the NMOS pull-down transistor. This reduction in majority carrier mobility occurs in response to an increase in temperature over a first operating temperature range. According to another embodiment of the present invention, the driver control circuit has a switchable pull-down path that extends between the gate of the first driver transistor and the reference power supply line. This switchable pull-down path includes a depletion mode transistor having a first current carrying terminal electrically coupled to the gate of the first driver transistor, which is preferably a PMOS pull-up transistor.
Still further embodiments of an integrated driver circuit include a first NMOS pull-down transistor and a first PMOS pull-up transistor connected together in a totem pole arrangement that extends between a positive power supply line and a reference power supply line. A gate of the first NMOS pull-down transistor and a gate of the first PMOS pull-up transistor may be connected together or independently controllable in the event a high impedance output condition is desired. A first driver control circuit is provided having a switchable pull-up path therein that extends between a gate of the first NMOS pull-down transistor and the positive power supply line. This pull-up path includes a first depletion mode transistor having a first current carrying terminal electrically coupled to the gate of the first NMOS pull-down transistor. The first depletion mode transistor may be a PMOS or NMOS depletion mode transistor having its gate and source terminals connected together. A second driver control circuit is also provided having a switchable pull-down path therein that extends between a gate of the first PMOS pull-up transistor and the reference power supply line. This pull-down path includes a second depletion mode transistor having a first current carrying terminal electrically coupled to the gate of the first PMOS pull-up transistor.
The first and second depletion mode transistors are preferably buried channel devices having improved mobility characteristics resulting from reduced Si/SiO2 interface scattering. It is also preferred that these buried channel devices have a peak channel dopant concentration therein at a level of about 1xc3x971018 cmxe2x88x923 or less to reduce phonon scattering and impurity scattering. To achieve preferred device characteristics by reducing ground bounce, the ldsat(NMOS) characteristics of the NMOS pull-down transistor should be made independent of temperature. This can be achieved by designing the first depletion mode transistor to compensate for reductions in mobility (and reductions in ldsat(NMOS)) within the NMOS pull-down transistor. In particular, the first depletion mode transistor is designed to have temperature dependent ldsat characteristic that meets the following relationship over at least a first portion of an operating temperature range: 0.005xe2x89xa6∂ldsat/∂Txe2x89xa60.015, where T designates a temperature (xc2x0 C.) within the operating temperature range. This temperature dependent characteristic of the first depletion mode transistor can be used to compensate for an NMOS pull-down transistor having a temperature dependent ldsat(NMOS) characteristic that meets the following relationship over at least a second portion of the operating temperature range: xe2x88x920.01xe2x89xa7∂ldsat(NMOS)/∂Txe2x89xa7xe2x88x920.015.
The switchable pull-up path also includes a second PMOS pull-up transistor having a drain electrically connected to a second current carrying terminal of the first depletion mode transistor and a source electrically connected to the positive power supply line. The switchable pull-down path also includes a second NMOS pull-down transistor having a drain electrically connected to a second current carrying terminal of the second depletion mode transistor and a source electrically connected to the reference power supply line. A third NMOS pull-down transistor is provided that is electrically coupled to the pull-up path. The third NMOS pull-down transistor preferably has a drain electrically connected to the first current carrying terminal of the first depletion mode transistor. A third PMOS pull-up transistor is provided that is electrically coupled to the pull-down path. The third PMOS pull-up transistor preferably has a drain electrically connected to the first current carrying terminal of the second depletion mode transistor. A gate of the third NMOS pull-down transistor and a gate of the second PMOS pull-up transistor may be electrically connected together and responsive to a first input signal. A gate of the third PMOS pull-up transistor and a gate of the second NMOS pull-down transistor may be electrically connected together and responsive to a second input signal.
To improve speed characteristics, first and second bootstrap capacitors are provided. The first bootstrap capacitor has a first electrode electrically connected to a second current carrying terminal of the first depletion mode transistor and a second electrode electrically connected to the first current carrying terminal of the first depletion mode transistor. The second bootstrap capacitor has a first electrode electrically connected to a second current carrying terminal of the second depletion mode transistor and a second electrode electrically connected to the first current carrying terminal of the second depletion mode transistor. The first and second bootstrap capacitors are preferably sized to achieve fast turn on of the first NMOS pull-down transistor and first PMOS pull-up transistor, respectively.